DC Offset Cancellation Circuits and Methods

ABSTRACT

Embodiments of the present invention include circuits and methods for reducing DC Offset. In one embodiment the present invention includes storing DC offset on internal capacitances. In one embodiment, parallel stages are used to remove DC offset corresponding to different local oscillator frequencies. Embodiments of the invention further include changing the low cutoff frequency of the DC cancellation circuits for fast calibration. In a first state, a high pass filter may have a first low cutoff frequency, and in a second state the high pass filter may have a second cutoff frequency lower than the first low cutoff frequency. The present invention also includes a variable gain amplifier with reduced DC offset.

CROSS REFERENCE TO RELATED APPLICATIONS

This application is a continuation of and claims the benefit of U.S.patent application Ser. No. 11/112,174, filed Apr. 22, 2005, entitled“DC Offset Cancellation Circuits and Methods,” naming Edris Rostami,Rahim Bagheri, Masoud Djafari, and Alireza Mehrnia as inventors.

BACKGROUND

The present invention relates to reducing the effects of DC offset inelectronic systems, and in particular, to circuits and methods that maybe used to reduce DC offset in an electronic system such as a wirelessreceiver.

Electronic systems often include many different components that operateusing voltages and currents, which are typically characterized accordingto whether or not they change periodically over time. Voltages andcurrents that do not change periodically over time are referred to as“direct current” (“DC”) signals, and voltages and currents that dochange periodically over time are referred to as “alternating current”(“AC”) signals. FIG. 1 illustrates an AC signal, a DC signal and DCoffset. FIG. 1 shows three waveforms. Waveform 101 is a purely ACwaveform because the voltage, V1, varies periodically (in this case,sinusoidally) over time and is centered on zero volts. Waveform 102 is apurely DC waveform because it maintains the same voltage, V2, over time.Waveform 103 illustrates an AC waveform with a DC offset. Waveform 103varies with time, but it is shifted to a voltage V3. In this case,waveform 103 is a sinusoid that is offset by a voltage V3. FIG. 2illustrates the frequency spectrum of an AC waveform with a DC offsetsuch as waveform 103. For instance, waveform 103 may be a sinusoidalsignal oscillating at a frequency of f1. Therefore, as shown in FIG. 2,waveform 103 will have a frequency component at f1 and another componentat zero frequency (i.e., DC).

In many electronic systems it is desirable to process only the ACcomponents of signals and not the DC component. FIG. 3 illustrates anamplifier circuit that processes both the AC and DC components of asignal. Amplifier 300 may receive a varying voltage Vin as an input andgenerate an output Vout that is an amplified version of the input. Inthis example, Vin is a sinusoidal signal with a peak-to-peak amplitudeof 400 mV and a DC offset of 1 volt. If amplifier 300 provides a gain of10, the output Vout will be a sinusoidal signal having a peak-to-peakamplitude of 4 volts and a DC offset of 10 volts.

FIG. 4 illustrates one of the problems caused by DC offsets in anelectronic circuit. Non-ideal amplifiers require a power supply Vdd andoften include some inherent DC offset. For example, amplifier 400 ispowered by a 12 volt supply and has an input referred DC offset of 150mV, which will increase the DC offset of an input signal Vin by 1.5volts if amplifier 400 has a gain of 10. Thus, if amplifier 400 receivesa sinusoidal signal with a peak-to-peak amplitude of 400 mV and a DCoffset of 1 volt, the output should be a sinusoidal signal with apeak-to-peak amplitude of 4 volts and a DC offset of 11.5 volts.However, since the power supply Vdd of amplifier 400 is only 12 volts,the output signal cannot swing to its maximum value of 13.5 volts (i.e.,11.5 v+2 v) because the amplifier output is limited to a maximum valueof Vdd (often less). Consequently, the output signal will reach amaximum value of 12 volts, which is referred to as “clipping.” Thus, theDC offset introduced by amplifier 400 can result in severe distortion ofthe AC component of the signal. This is just one of many problems causedby unwanted DC offsets.

FIGS. 5A-B illustrate problems caused by DC offset in ananalog-to-digital converter. In this example, amplifier 510 receives aninput signal Vin and provides an analog output signal Vout to the inputof analog-to-digital converter (“ADC”) 520. ADC 520 converts the analogsignal into binary (i.e., digital) values carried by N digital signallines (i.e., where N is an integer). Both amplifier 510 and ADC 520 may,but not necessarily, be powered by the same supply Vdd. To optimize theconversion of the analog signal, it is desirable to use the full rangeof the ADC. When the full range is used, more bits are available torepresent the analog input signal values. However, when the full rangeis not used, fewer bits are available to represent the analog signalvalues, and the digital representation of the signal is less accurate.The range of the ADC is optimized by making Vout as close to the fullrange of the ADC as possible (the full range of an ADC is typically, butnot necessarily, a little less than Vdd).

FIG. 5B illustrates two signals 501 and 502. Signal 501 is a sinusoidalsignal with a DC offset of one-half Vdd (“half-supply”). If the fullrange of the ADC is from zero volts to Vdd, then signal 501 may beaccurately converted because signal 501 varies substantially across thefull range, which in this case is an equal amount both above and belowhalf-supply. However, as illustrated by signal 502, when an unwanted DCoffset is introduced in a signal, the signal cannot use the full rangeof the ADC. For instance, signal 502 is a sinusoidal signal with a DCoffset of three-fourths Vdd (i.e., 3Vdd/4). Therefore, signal 502 islimited to a maximum amplitude of one-fourth Vdd. Consequently, half therange of the ADC is lost because of the DC offset.

DC offsets are caused by a variety of phenomena. One source of DC offsetis from second order harmonics generated by components of an electronicsystem. For example, if a transistor receives a sinusoidal input signalVin (e.g., on a gate terminal), the output signal Vout (e.g., on a drainterminal) will typically include some harmonic distortion. The followingequations represent the output of an electronic component as a series toillustrate DC offset generated by harmonic distortion:

Vout=AVin+BVin² +CVin³+ . . .

If the input, Vin, is a sinusoidal signal having a frequency ω_(c),then:

Vout=A Sin(ω_(c) t)+B Sin²(ω_(c) t)+C Sin³(ω_(c) t)+ . . .

Referring to the second term above, which is the second harmonic, the DCoffset can be seen as follows:

B Sin²(ω_(c) t)=B[½−Cos(2ω_(c) t)/2]

It can be seen that the second harmonic introduces a DC component ofB/2. Thus, second order harmonic is one source of DC offset in anelectronic system.

Another source of DC offset in electronic systems is mismatch betweenelectronic components. For example, if resistors are mismatched in adifferential system, bias currents through the different resistances mayproduce a constant voltage difference in the system. More generally,mismatches between electronic components in amplifiers, current sourcesand other electronic circuits may cause the components operate atdifferent DC operating points. These non-ideal operational conditions ofthe components often result in a DC offset in the system.

DC offset is an important factor in many applications, but it isparticularly important in the design and operation of wirelessreceivers. FIG. 6 illustrates an existing technique for reducing DCoffset in a “direct conversion” wireless receiver. Wireless receiver 600includes an antenna 610 for receiving RF signals. Antenna 610 is coupledthrough a switch 601 to a low noise amplifier 611 (“LNA”), mixer 612,filter 614, variable gain amplifier 615 (“VGA”) and analog-to-digitalconverter 616 (“ADC”). LNA 611 is used for amplifying high frequencysignals from antenna 610 and must have sufficient bandwidth, gain andnoise performance to meet system requirements. The local oscillatorsignal (“LO”) is generated by frequency synthesizer 630. Mixer 612receives a local oscillator signal (“LO”) at the carrier frequency anddown converts the input signal. Filter 614 is used to extract the signalof interest from the down converted signal, and VGA 615 providesappropriate gain so that the input to ADC 616 is optimizing the ADC'sfull range. The output of the reception channel is coupled to basebandprocessor 620 over N-bit digital signal lines, for example, for decodingand further processing.

DC offset in a wireless receiver may have many sources in addition tothe sources described above. For example, one source of DC offset isfrom unwanted coupling (sometimes referred to as “leakage” or“feedthrough”) of the local oscillator (“LO”) signal into other parts ofthe receiver. The LO signal is typically a strong signal, and as suchmay couple into the communication channel and back into antenna 610. TheLO signal may also couple to the input of LNA 611. In both cases the LOsignal is boosted by the high gain of the LNA and, consequently,received by mixer 612 on both inputs. This is referred to as“self-mixing.” Self-mixing may also occur when the LO signal couplesdirectly to the input of mixer 612. When the LO signal self-mixes withitself, the DC offset voltage generated at the output of mixer 612 maybe very large. For instance, when the LO signal is received on bothinputs of mixer 612, the LO signal is multiplied by itself. The DCoffset generated by this phenomena can be seen from the followingequations wherein the LO signal is modeled as a sinusoidal signal havinga frequency ω_(c):

Vout  mixer = V in 1 * V in 2V out  mixer = Sin(ω_(c)t)Sin(ω_(c)t); self-mixing         = Sin²(ω_(c)t)         = [1 − Cos(2ω_(c)t)]/2         = 1/2 − Cos(2ω_(c)t)/2

Thus, the mixer output includes a constant component (i.e., ½) that haszero frequency. This term represents a DC offset at the output of themixer resulting from self-mixing of the LO signal. Similarly, frequencycomponents of the RF input signal may couple from the input channel tothe LO input of the mixer. Such components will also self-mix and resultin additional DC offset at the mixer output.

DC offset at the output of the mixer in a wireless receiver can havesevere consequences on system performance. Typically, wireless receiversare designed to detect very low level signals, and therefore typicallyhave very high gain. VGA 615, for example, may have a gain of 50 dBv ormore (i.e., dBv=20 log₁₀(Vout/Vin)), which would increase a DC offset atthe mixer output by a factor of over 300. Moreover, in some applicationsan ADC may have a power supply as low as Vdd=1.2 v or less, with adynamic range on the order of hundreds of millivolts (e.g., 250 mV).Therefore, for accurate conversion of the analog signal, a maximum DCoffset of less than a hundred millivolts may be required. This wouldresult in a maximum allowable DC offset at the mixer output of less thana few hundred microvolts. For example, for a maximum allowable offset of75 mV at the input of the ADC, the maximum DC offset at the output ofthe mixer would be about 250 μV for a VGA with a gain of 300. Whilethese values are only an example, they clearly illustrate the importanceof DC offset cancellation in electronic systems such as a wirelessreceiver. DC offset cancellation (i.e., DC offset reduction) is thus animportant consideration in the design of electronic systems.

FIG. 6 further illustrates one existing approach to removing DC offsetfrom a wireless receiver. According to this approach, the system iscalibrated during a calibration cycle using a feedback loop. During thecalibration cycle, the ADC measures the DC offset and passes the DCoffset value as a digital signal to baseband processor 620. Basebandprocessor, in turn, provides a DC offset feedback signal to adigital-to-analog converter 621 (“DAC”). The output of the DAC issubtracted off the DC offset in the channel at 622. There are manydisadvantages to the DC offset cancellation approach shown in FIG. 6. Inparticular, feedback loops can be slow, unstable and have limitedaccuracy. For instance, feedback loops always have some inherent delayaround the loop, and some applications may require that the DC offset beeliminated within a period of time that is too short to accommodate suchdelays. Additionally, as the speed of a closed loop system is increased,such systems tend to become less stable. Moreover, accuracy of existingapproaches may be compromised by the limited resolution of the ADCsampling the DC offset, as well as by the accuracy with which thedigital system compensates for the DC offset (e.g., if the digitalsystem generates a DC signal to subtract from the DC offset, theaccuracy of the DC signal may be limited by the digital-to-analogconversion process). Furthermore, if DC offset varies with gain,calibration would require a different correction for each possible gainsetting, which will make the system much more complex.

Thus, there is a need for improved circuits and methods for reducing DCoffset, and in particular, for improved circuits and methods that may beused to reduce DC offset in wireless receivers.

SUMMARY

Embodiments of the present invention include circuits and methods forreducing DC offset. In one embodiment the present invention includesstoring DC offset on internal capacitances. In one embodiment, parallelstages are used to remove DC offset corresponding to different localoscillator frequencies. Other embodiments of the invention include DCoffset cancellation circuits with changing cutoff frequencies that maybe used to calibrate DC offsets in a very short period of time. In afirst state, a the circuits may have a first cutoff frequency, and in asecond state the circuits may have a second cutoff frequency lower thanthe first cutoff frequency. In another embodiment, the present inventionincludes a variable gain amplifier circuit including a fixed gainamplifier followed by a DC offset cancellation circuit followed by anattenuator to reduce the effects of DC offset.

In one embodiment, the present invention includes a wireless receivercomprising a mixer having a first input, a second input and an output,wherein the first input is coupled to a first amplifier to receive anamplified RF signal and the second input is coupled to a frequencysynthesizer to receive a first signal having one of a plurality offrequencies, and a plurality of parallel DC offset cancellation stagesselectively coupled to the mixer output, wherein if the first signal hasa first frequency, then a first one of the plurality of parallel DCoffset cancellation stages is coupled to the mixer output, and if thefirst signal has a second frequency, then a second one of the pluralityof parallel DC offset cancellation stages is coupled to the mixeroutput.

In another embodiment, the present invention includes a wirelessreceiver comprising a first DC offset cancellation circuit, wherein in afirst state, the first DC offset cancellation circuit has a first lowcutoff frequency, and in a second state, the first DC offsetcancellation circuit has a second low cutoff frequency less than thefirst low cutoff frequency. In one embodiment, the first DC offsetcancellation circuit is coupled between a mixer and a variable gainamplifier. In another embodiment, the variable gain amplifier includesat least one second DC offset cancellation circuit, wherein in the firststate, the second DC offset cancellation circuit has a third low cutofffrequency greater than the first low cutoff frequency of the first DCoffset cancellation circuit, and in the second state, the second DCoffset cancellation circuit has a fourth low cutoff frequency less thanthe third low cutoff frequency.

In yet another embodiment, the present invention includes wirelessreceiver including a DC offset cancellation circuit, the DC offsetcancellation circuit comprising a capacitor having a first terminalcoupled to receive an input signal and a second terminal, a first MOStransistor having a first terminal and a second terminal, the firstterminal of the MOS transistor being coupled to the second terminal ofthe capacitor, and a resistance coupled between the second terminal ofthe first MOS transistor and a reference voltage, wherein, in a firststate, the resistance has a first value so that the circuit has a firstlow cutoff frequency, and in a second state, the resistance has a secondvalue so that the circuit has a second low cutoff frequency less thanthe first low cutoff frequency.

The following detailed description and accompanying drawings provide abetter understanding of the nature and advantages of the presentinvention.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates an AC signal, a DC signal and DC offset.

FIG. 2 illustrates the frequency spectrum of an AC waveform with a DCoffset.

FIG. 3 illustrates an amplifier circuit that processes both the AC andDC components of a signal.

FIG. 4 illustrates one of the problems caused by DC offsets in anelectronic circuit.

FIGS. 5A-B illustrate problems caused by DC offset in ananalog-to-digital converter.

FIG. 6 illustrates an existing technique for reducing DC offset in adirect conversion wireless receiver.

FIG. 7 illustrates a wireless receiver including DC offset cancellationaccording to one embodiment of the present invention.

FIGS. 8A-B illustrate another DC offset phenomena addressed byembodiments of the present invention.

FIG. 9 illustrates a DC offset cancellation circuit according to oneembodiment of the present invention.

FIGS. 10A-B are example implementations of a DC offset cancellationcircuit according to one embodiment of the present invention.

FIG. 11 illustrates another constraint on DC offset cancellationcircuits solved by embodiments of the present invention.

FIGS. 12A-B illustrate a DC offset cancellation circuit according toanother embodiment of the present invention.

FIG. 13 is an example of a differential implementation of a three stageDC offset cancellation circuit according to one embodiment of thepresent invention.

FIG. 14A illustrates a DC offset cancellation circuit according toanother embodiment of the present invention.

FIGS. 14B-D illustrate a DC offset cancellation circuit according toanother embodiment of the present invention.

FIG. 15 illustrates another embodiment of the present invention.

FIG. 16 is an example implementation of DC offset cancellation stageswith variable attenuation according to another embodiment of the presentinvention.

FIG. 17 illustrates part of a variable gain amplifier circuit accordingto one embodiment of the present invention.

FIG. 18A illustrates part of a VGA with a DC offset cancellation circuitaccording to one embodiment of the present invention.

FIG. 18B illustrates part of a VGA with a DC offset cancellation circuitaccording to another embodiment of the present invention.

FIG. 19 illustrates wireless receiver with DC offset cancellationaccording to another embodiment of the present invention.

DETAILED DESCRIPTION

Described herein are techniques for reducing DC offset in electronicsystems. In the following description, for purposes of explanation,numerous examples and specific details are set forth in order to providea thorough understanding of the present invention. In particular, manyof the techniques herein are very complex and are advantageouslydescribed using specific examples, such as wireless receivers andultra-wideband (“UWB”) wireless receivers, to illustrate certainadvantages of various embodiments. Therefore, many of the techniques aredescribed in a wireless receiver application. However, it will beevident to one skilled in the art that embodiments of the presentinvention may be used in other applications. Thus, the inventions, asdefined by the claims, may include some or all of the features in theseexamples alone or in combination with other features described below.

FIG. 7 illustrates a wireless receiver including DC offset cancellationaccording to one embodiment of the present invention. Wireless receiver700 includes an antenna 710 for receiving a RF signal. An RF signalreceived on antenna 710 is coupled through switch 701 to a low noiseamplifier 711 (“LNA”). LNA 711 is used for amplifying high frequencysignals from antenna 710 and must have sufficient bandwidth, gain andnoise performance to meet system requirements. The gain of LNA 711 maybe adjustable, for example, between 10 dBv and 20 dBv. The output of LNA711 is coupled to one input of mixer 712. The reception channel mayinclude two mixers and parallel paths for both in phase and quadraturepaths (only one path is shown here). A local oscillator signal (“LO”) isgenerated by frequency synthesizer 730. Mixer 712 receives a localoscillator signal (“LO”) at the carrier frequency and down converts theinput signal. In this example, the system is a direct conversion system.In a direct conversion system, the input signal is down converted tobaseband, and no intermediate frequencies are used. However, the presentinvention is not limited to direct conversion systems. The output ofmixer 712 is coupled to filter 714. Filter 714 is used to extract thesignal of interest from the down converted signal. The present inventionincludes a DC offset cancellation circuit 715 between filter 714 and aVGA 715. The DC offset cancellation circuit reduces the DC offset fromupstream circuits (e.g., mixer 712 and LNA 711). VGA 715 receives thedown converted signal with reduced DC offset and provides appropriategain so that the input to ADC 716 is at the ADC's full range. In oneembodiment, VGA 715 may be a programmable gain amplifier (“PGA”) thatreceives digital gain control signals from another part of the system tochange the gain in discrete steps. As described in more detail below,embodiments of the present invention may include additional DC offsetcancellation circuits in VGA 715 for further reducing DC offset in thesystem. The output of the reception channel is coupled to basebandprocessor 720 over N-bit digital signal lines, for example, for decodingand further processing.

FIGS. 8A-B illustrate another DC offset phenomena addressed byembodiments of the present invention. FIG. 8A illustrates frequencyhopping. Some wireless systems may use multiple carrier frequencies thateach carry information of interest. FIG. 8A illustrates three carrierfrequencies f1, f2, and f3 used to carry information in threecommunication channels 801, 802, and 803. In a frequency hoppingtransmission scheme, the channel used to transfer information may changebetween the three channels 801, 802, and 803 during a singlecommunication event (e.g., communication of a data packet). Thus, thesystem may receive information on a first carrier frequency, f1, and thesynthesizer must generate an LO signal at f1 to down convert theincoming signal. After some time period, the system may change thechannel, and the synthesizer must change the frequency of the LO signalto extract the information received on the new channel (e.g., f2 onchannel 802). These frequency changes are sometimes referred to as“channel hopping,” and such changes between frequencies may occur in avariety of different patterns (e.g., f1-f2-f1-f2-f3 orf1-f3-f2-f1-f3-f2).

One problem caused by frequency hopping is that the different LO signalsused to down convert the different carrier frequencies can producedifferent DC offsets. FIG. 8B illustrates different DC offsets generatedat different frequencies f1, f2, and f3. When the system is receivinginformation on channel 801, and generating an LO signal having afrequency f1, the output of mixer 712 will have a DC offset of “DC1.”Similarly, when the system is receiving information on channel 802, andgenerating an LO signal having a frequency f2, the output of mixer 712will have a DC offset of “DC2.” Finally, when the system is receivinginformation on channel 803, and generating an LO signal having afrequency f3, the output of mixer 712 will have a DC offset of “DC3.”

In one embodiment, the present invention reduces DC offset caused bychannel hopping. FIG. 9 illustrates DC offset cancellation according toone embodiment of the present invention. DC offset cancellation circuit900 includes first, second, and third DC offset cancellation stages901-903 in parallel and control signals (“Select”) for controlling whichstage is active. For example, each DC cancellation stage may include aninternal capacitance (e.g., a capacitor) for storing different DCoffsets corresponding to different LO frequencies. Thus, when a receiveris receiving information on a first carrier frequency (e.g., f1 forchannel 801), the system activates DC offset cancellation stage 901 forcanceling DC offset corresponding to a first LO frequency. When areceiver is receiving information on a second carrier frequency (e.g.,f2 for channel 802), the system may activate DC offset cancellationstage 902 for canceling DC offset corresponding to a second LOfrequency. Finally, when the receiver is receiving information on athird carrier frequency (e.g., f3 for channel 803), the system activatesDC offset cancellation stage 903 for canceling DC offset correspondingto a third LO frequency. As illustrated below, each stage may beactivated by selectively coupling each stage to the mixer output, forexample, by closing internal switches in each circuit.

FIGS. 10A-B are example implementations of a DC offset cancellationcircuit according to one embodiment of the present invention. In oneembodiment, each DC cancellation stage includes a high pass filter. Forexample, in FIG. 10A three high pass filters are arranged in paralleland selectively coupled to the mixer output. When the system isreceiving a signal on a first channel, switch 1001 may be closed so thatthe input signal passes through high pass filter 1005. When the systemis receiving a signal on a second channel, switch 1002 may be closed sothat the input signal passes through high pass filter 1006. When thesystem is receiving a signal on a third channel, switch 1003 may beclosed so that the input signal passes through high pass filter 1007.

FIG. 10B is an example of one high pass filter configuration that may beused. The DC offset cancellation circuit in this example includes threeswitches 1001-1003 in series with three capacitors 1011-1013. Eachcapacitor is coupled to ground through a resistance 1015 (“R”). It isunderstood that ground is a reference voltage and other referencevoltages may be used. When switch 1001 is closed, the DC offset (“DC1”)generated at the mixer output corresponding to a first channel (i.e., afirst LO signal frequency) may be stored on capacitor 1011 (“C1”). Whenthe system “hops” to a new frequency and a new DC offset (“DC2”) isgenerated at the mixer output, switch 1001 is opened and switch 1002 isclosed. The new DC offset is stored on capacitor 1012 (“C2”). When thesystem “hops” to a yet another frequency and a third DC offset (“DC3”)is generated at the mixer output, switch 1002 is opened and switch 1003is closed. The third DC offset is stored on capacitor 1013 (“C3”). Aftereach DC offset is stored on capacitors C1-C3, the down converted signalsreceived from the mixer may be passed for further amplification inamplifier 1020, which may be the first stage of a VGA, for example.

FIG. 11 is an example of another constraint on DC offset cancellationcircuits solved by embodiments of the present invention. In wirelessapplications it is often desirable to calibrate DC offset at thebeginning of a communication event. If DC offset is calibrated beforesuch an event (i.e., while the system is idle), incoming data may belost if the data is received while the system in the middle of acalibration cycle. Moreover, calibrated DC levels may need to beperiodically refreshed if the system remains idle for an extended periodof time. Features and advantages of the present invention include fastcalibration of DC offsets at the beginning of a communication event. Forexample, FIG. 11 shows a preamble 1101 and payload 1102 of an incomingpacket in a packet based protocol received by a wireless system at thebeginning of a communication. The preamble may be used forsynchronization, determining a frequency hopping pattern, and gainadjustment, for example. An example preamble may include 21 symbols 1110that are each about 310 ns in duration, such as is found in an 802.15protocol. Each symbol may include a plurality of subcarriers spreadacross a frequency range, such as orthogonal frequency divisionmultiplexing (“OFDM”) signals. Moreover, each symbol may be received ona different frequency channel, and the first symbol may indicate to thereceiving system when and how the frequency channels will change (i.e.,the first symbol may contain the frequency hopping pattern indicatingwhen the incoming signal will change channels and what the next channelwill be). As symbols in the preamble are received, the system may gothrough a calibration cycle and change the gain of the receiver.However, while the system is receiving the preamble, DC offset shouldnot cause too much signal loss or distortion (e.g., if the receiverbecomes saturated) or else the gain adjust and other preamble functionswill not be completed accurately. Accordingly, DC offset must becancelled quickly during reception of the preamble. For instance, someapplications may only allocate 10 or 20 percent of each symbol (e.g.,about 40-66 ns) for DC offset circuits to complete the DC cancellationprocess. Moreover, some embodiments may require that the receiverprocess signals while the DC offset circuits are in the process ofcalibrating the unwanted DC offsets.

FIGS. 12A-B illustrate a DC offset cancellation circuit according toanother embodiment of the present invention. FIG. 12A shows a DC offsetcorrection circuit 1200 that may be used in one channel of themulti-channel circuit of FIG. 9, and includes additional circuitry forDC offset cancellation, for example, when the system is receivingsymbols. In one embodiment, the DC offset cancellation circuit operatesin two states. In the first state (e.g., a calibration state), thecircuit is configured to have a first low cutoff frequency high enoughto allow the circuit to accurately capture the DC offset in a short timeperiod. In the second state, the circuit is configured to have a secondlow cutoff frequency low enough to pass all frequencies of interest. Forexample, the low cutoff frequency (sometimes referred to as the “cornerfrequency”) of the high pass filter circuit of FIG. 12A is as follows:

f _(c)=1/2πRC

ω_(c)=1/RC

where C is the capacitance of C2 and R is the resistance determined byresistors 1215 (“R1”) and 1216 (“R2”).

When the system is receiving information on a first frequency channel,the system may close switches 1201 and 1202, thereby placing the circuitin the signal path and further configuriing R1 and R2 in parallel. Sincethe resistance of a parallel combination of resistors R1 and R2 is lessthan the resistance of R1 alone, the low cutoff frequency increases whenswitch 1202 is closed (i.e., R decreases so f_(c) increases). If DCoffset from the mixer causes an increase in the voltage on capacitor1212 (“C2”), such increase will cause a corresponding increase on thefilter output. However, the output of the filter will discharge back tozero volts through resistors R1 and R2. It is desirable to accuratelystore the DC offset on capacitor C2. Therefore, it is desirable to allowthe output to discharge as close to zero volts as possible. The settlingtime of the circuit is governed by the time constant, τ. If a timeperiod of 6τ passes, for example, the output will be very close toground, and the DC correction voltage stored on C2 will be very close tothe DC offset of the mixer. Since the time constant of the circuit isgiven by τ=RC, increasing the low cutoff frequency (e.g., by configuringR1 and R2 to be in parallel) has the effect of reducing the timeconstant, and therefore, reducing the time that is needed to accuratelystore the DC offset on the capacitor. Thus, during DC offset correction,the low cutoff frequency of the circuit may be increased so that the DCoffset is accurately stored on capacitor C2.

However, increasing the low cutoff frequency may also cause a loss ofinformation. As shown in FIG. 12B, some information carrying signals(e.g., s1 and s2) may be below the low cutoff frequency of the circuitduring DC offset calibration. Some applications may tolerate the loss ofsome information carrying signals during the calibration cycle, butrequire that such signals not be lost during normal operation.Accordingly, after a predetermined time period when the DC offset isstored on capacitor C2, the system may reconfigure the circuit to have asecond cutoff frequency low enough to pass all frequencies of interest.For example, in a second state, the system may open switch 1202, therebyincreasing R and reducing the low cutoff frequency. As shown in FIG.12B, the low cutoff frequency moves from ω_(c1), to ω_(c2). Thus, allthe information carrying signals may pass through the circuit (e.g., s1and s2 will be above the cutoff frequency in the second state ratherthan below the cutoff frequency as in the first state). It is to beunderstood that a variety of low cutoff frequencies may be used toreduce the RC time constant of the circuit or pass signals of interest,and a variety of time periods may be used to accurately capture the DCoffset. Such implementation details will be matters of design choicegoverned by the design requirements of the application.

An example application of this technique is in a wireless receiver thatreceives 21 symbols in a preamble at the beginning of each communicationtransaction. In one application, each symbol is 310 ns, and differentsymbols may be received on different carrier frequencies (i.e.,different LO frequencies are used to down convert the incoming RF signalcarrying different symbols). For instance, the first symbol may bereceived on carrier frequency f1, the second symbol may be received oncarrier frequency f2 and the third symbol may be received on carrierfrequency B. In some cases, other frequency hopping patterns are usedsuch as [f1, f3, f1, f3, f2] or [f1, f1, f2, f2, f3, f3], for example.Moreover, each symbol may include a plurality of subcarriers (e.g., s1,s2, . . . , sN) spaced at certain frequency intervals (e.g., 4.125 MHz).The subcarriers may carry information, for example, by encoding two databits {a, b} as follows:

s1=sin(2πf ₁ t+φ)

wherein an example of the data encoding is as follows:

{0,0}→φ=0

{0,1}→φ=π/2

{0,0}→φ=π

{1,1}→φ=3π/2

During a calibration cycle, this data may be used to configure thesystem to accurately receive the payload. Thus, during a calibrationcycle, the DC offset must be corrected, but in the process of correctingfor DC offset, data cannot be lost or else the system will not be ableto receive the data encoded in the subcarriers.

For this example, DC offset may be captured on capacitor C2 for a firstportion of the symbol (e.g., about the first 20% of the symbol, which is20% of 310 ns, or about 66 ns). Therefore, when the first symbol isreceived, the DC offset correction circuit will initially be configuredin a first state wherein the time to accurately store the DC offset onthe capacitor is less than a predetermined portion of the total symboltime. In particular, switch 1202 may be closed so the resistance toground is reduced and the time constant of the circuit reduced (i.e.,the low cutoff frequency is increased). Resistors R1 and R2 andcapacitor C2 may be selected so the time to accurately store the DCoffset is less than about 20% of the symbol time (e.g., 6τ=6RC).

Additionally, the RC time constant will also set the cutoff frequency ofthe circuit. If the RC time constant is too low, the correspondingcutoff frequency will be very high and cause more of the subcarriers tobe lost. Therefore, R1, R2 and C2 should be selected so that the RC timeconstant is low enough to allow sufficiently fast and accurate storageof the DC offset on capacitor C2, but high enough to result in a cutofffrequency that allows as many of the subcarriers to pass as possible. Inone embodiment, R1, R2 and C2 are selected so that the cutoff frequencyin the first state is about 15 Mhz, which only impacts subcarriers belowthat frequency, and the 6τ=6RC point is about 66 ns. Thus, after thisportion of the symbol time, the system may receive the information inthe first symbol above the cutoff frequency. It is to be understood thatthe cutoff frequency and time constant are only examples and that avariety of other implementations may be used depending on therequirements of the particular system.

After a predetermined time period during which the DC offset is storedon capacitor C2, the system may reconfigure circuit 1200 into a secondstate by opening switch 1202, and thereby removing R2 from the circuit.In the second state, the DC offset is removed from the signal pathbecause such offset is stored on capacitor C2. However, the cutofffrequency is reduced because R2 is no longer in parallel with R1. Thus,in the second state, the cutoff frequency is below all the subcarriers,and all the subcarriers may pass through circuit 1200. In oneembodiment, the cutoff frequency in the second state may be 1 Mhz.

As mentioned above, the first symbol, or even the first two symbols, maybe received on a first carrier frequency f1, but the system may changeto other carrier frequencies f2 or f3 to carry other symbols. As alsodescribed above, this frequency hopping may cause the DC offset tochange. Accordingly, the DC offset cancellation process using multiplelow cutoff frequencies may be applied to each new carrier frequencyreceived by the system, so that the new DC offset generated from downconversion of a new carrier frequency can be eliminated. For example, ifthe hopping pattern is [f1, f2, f3, f1, f2, f3, . . . ], then the systemwill reconfigure itself to receive the second symbol at frequency f2 bydeactivating a first DC offset correction circuit and activating asecond DC offset correction circuit. For the third symbol, the systemwill reconfigure itself to receive the third symbol at frequency f3 bydeactivating the second DC offset correction circuit and activating athird DC offset correction circuit.

In one embodiment, the system may reconfigure between the first cutofffrequency and the second lower cutoff frequency after all DC offsetcancellation circuits have stored DC calibration voltages. For example,in one approach, all of the DC offset cancellation circuits may beconfigured in the first state until each channel in a frequency hoppingpattern has been received and DC offsets corresponding to each frequencyhave been calibrated. When the last channel has been calibrated, thesystem may then reconfigure into the second state. A specific examplemay be if the frequency hopping pattern were [f1, f2, f3, f2, f3, f1, .. . ]. In this case, the system would be in the first state while thesystem is receiving the first three frequencies (i.e., after the firstoccurrence of f1, f2, and f3, and the system may reconfigure after thefirst pattern cycle (here, after the third symbol). If the pattern were[f1, f1, f2, f2, f3, f3, f1, . . . ], for example, the system mayreconfigure after the fifth symbol (i.e., after the first occurrence off3 has been calibrated).

In another embodiment, each channel may reconfigure after apredetermined time period of each symbol when the DC calibration voltagefor that symbol frequency has been stored on the capacitor. For example,if the frequency hopping pattern is [f1, f2, f1, f2, f3, f1, . . . ],then during a first portion of the first symbol the circuit will enter afirst state to store the DC offset corresponding to the first carrierfrequency, f1, on an internal capacitance, and during a second portionof the first symbol the circuit will enter a second state with a lowercutoff frequency to allow subcarriers to pass unattenuated. Then, duringa first portion of the second symbol the circuit will enter a firststate to store the DC offset corresponding to the second carrierfrequency, f2, on an internal capacitance, and during a second portionof the second symbol the circuit will enter a second state with a lowercutoff frequency to allow subcarriers to pass unattenuated. During afirst portion of the third symbol the circuit will enter a first stateto store the DC offset corresponding to the third carrier frequency, f3,on an internal capacitance, and during a second portion of the thirdsymbol the circuit will enter a second state with a lower cutofffrequency to allow subcarriers to pass. It can be seen that otherhopping patterns may be used. For example, if the hopping pattern is[f1, f1, f2, f2, f3, f3, f1, f1, f2, . . . ], then the system will storeDC offsets on the first, third and fifth symbols. More generally, thesystem will store a DC offset for a first portion of each input signalat each carrier frequency and apply the stored DC offset to subsequentuses of that carrier frequency. It is to be understood that otherimplementations may use other similar techniques to store DC offsets andchange cutoff frequencies between different portions of input signals inaccordance with different requirements of particular applications. Inaddition to the other features and advantages described above, thistechnique is also advantageous because the lower cutoff frequency in thesecond state (e.g., 1 Mhz) will automatically eliminate any lowfrequency phenomena effecting DC offset with a frequency below suchcutoff frequency.

FIG. 13 is an example of a differential implementation of a three stageDC offset cancellation circuit 1300 according to one embodiment of thepresent invention. Circuit 1300 includes three parallel stages forremoving DC offset generated, for example, as a result of using threedifferent LO frequencies to down convert three different carrierfrequencies. The first stage includes transistor 1301 acting as a switchand capacitor 1321 (“C1”) on the positive side and transistor 1302 andcapacitor 1322 (“C2”) on the negative side. Capacitor C1 is coupled toground through resistor 1315 (“R1”). A second resistor 1316 (“R2”) maybe configured in parallel with R1 to reduce the time for a DC offset tobe stored on C1. Capacitor C2 is similarly coupled to ground throughresistor 1317, which is designated “R1” so that the circuit issymmetric. A second resistor 1318 (“R2”) may be configured in parallelwith resistor 1317 to reduce the time for a DC offset to be stored onC2. In a first state, switches 1301 and 1302 are closed and the circuitstores DC offset on C1 and C2 (i.e., +DC1 and −DC1). In a second state,switches 1301 and 1302 may be opened to reduce the low cutoff frequencyof the circuit.

Similarly, circuit 1300 includes a second DC offset cancellation stageincluding transistor switches 1303-1304 and capacitors 1323-1324 (“C3”and “C4”) for storing a second DC offset (i.e., +DC2 and −DC2). Thethird DC offset cancellation stage includes transistor switches1305-1306 and capacitors 1325-1326 (“C5” and “C6”) for storing a thirdDC offset (i.e., +DC3 and −DC3). Transistors 1301-1306 may be used toselectively couple each DC offset cancellation stage into the signalpath and thereby store different DC offsets. Since the voltages on theresistors are allowed to discharge close to ground, signals passingthrough the capacitors of each stage will undergo a DC shift from +/−DCto ground. The DC offset at the output of circuit 1300, Vout diff,therefore, may be substantially eliminated.

The accuracy of circuit 1300 may be improved by observing that certainfactors can affect the DC offset stored on each capacitor. For example,transistor switches 1301 and 1302 will experience differentgate-to-source and gate-to-drain voltages. In particular, transistors1301 and 1302 may have the same gate voltages, but transistor 1301 mayhave source and drain voltages at +DC1, while transistor 1302 has sourceand drain voltages at −DC1. Such voltage differences may result indifferent charge injection as the transistors are turned off and on,which will cause the voltages on capacitors C1 and C2 to change bydifferent amounts, resulting in a net DC offset.

FIG. 14A illustrates a DC offset cancellation circuit 1400A according toanother embodiment of the present invention. According to thisembodiment, the switches coupling each DC offset cancellation stage intothe signal path (e.g., to the mixer output) are moved to the other sideof the capacitors. For example, each stage may be selectively coupled tothe mixer output by closing a switch, which couples the output of the DCoffset cancellation stage into the signal path, and each stage may beselectively decoupled from the mixer output by opening a switch, whichmay cause components in the DC offset cancellation circuit to be an opencircuit. In FIG. 14A, the input of the circuit is coupled to a firstplate of a capacitor, the other plate of the capacitor is coupled to oneterminal of a switch (e.g., a source terminal of a transistor), and theother terminal of the switch (e.g., a drain terminal of a transistor) iscoupled to the output. Circuit 1400A shows one stage of such a circuit.Capacitors 1421 (“C1”) and 1422 (“C2”) are coupled to a differentialinput that may have a DC offset of +/−DC1. The other terminals ofcapacitors C1 and C2 are coupled to source terminals of transistorswitches 1401 and 1402. The drain terminals of transistor switches arecoupled to the outputs. In the examples described here and above,wherein the resistors are shared by each DC offset cancellation stage,the drain terminals of transistors 1401 and 1402 are coupled toresistors 1415-1416 and 1417-1418, respectively, which are in turncoupled to a bias voltage Vb (bias voltage Vb is used as a referencevoltage for the differential circuit). If each stage used separateresistors, such resistors may be coupled to the source of the switchtransistors 1401 and 1402. In circuit 1400A, transistor switches 1401and 1402 will both discharge close to the bias voltage Vb during a DCoffset calibration. Therefore, when the system switches betweendifferent DC offset cancellation stages, the source and drain terminalsof both transistors 1401 and 1402 should be very close to the biasvoltage Vb, which is AC ground. Since both transistors will haveapproximately the same source and drain voltages with respect to ground,the charge injection introduced by both devices will be about the same,and the DC offset resulting from charge injection will be reduced.

Charge injection effects may be further reduced by addressing two otherphenomena. First, device and component mismatch may be a further causeof DC offset. For instance, if switches 1401 and 1402 in circuit 1400Aare mismatched, they may inject different amounts of charge. Moreover,the charge injected by such devices may produce different voltages ifthe capacitors and resistors (e.g., R1, R2, C1 and C2) are alsomismatched. Such mismatch may be caused by device or component dimensionvariations during fabrication, for example. The DC offsets generated bythese mismatches may be exacerbated by the input capacitances on thenext stage of the system.

FIGS. 14B-D illustrate a DC offset cancellation circuit 1400B accordingto another embodiment of the present invention. Circuit 1400B includesswitches 1401A and 1402A and dummy devices 1401B and 1402B. Dummydevices 1401-1402B may have one-half (½) the capacitance of switchtransistors 1401-1402A (e.g., W/L of the dummy device is about ½(W/L) ofthe switch transistor). As shown in FIG. 14C, the source and drainterminals of the mismatch devices 1401B and 1402B are coupled together.Switch device 1401A only injects about one-half of its charge into theoutput of the circuit (i.e., the input “IN1” of the next stage). Sincedummy device 1401B is one-half the size of device 1401A, and since dummydevice 1401B injects all of its charge into the output node (i.e.,because the source and drain of the dummy device are coupled together),charge injection of the devices 1401A and 1401B may be cancelled byturning off the dummy device when the switch device is turned on andturning on the dummy device when the switch device is turned off. Asshown in FIG. 14C, the switch device 1401A is controlled by a signal “φ”and dummy device 1401B may be controlled by a signal “ φ”, which is thecomplementary signal to “φ”. FIG. 14D illustrates that dummy device1401B also reduces switching feedthrough (sometimes referred to as clockfeedthrough). As the voltage on the gate of device 1401A increases(i.e., as a voltage is applied across the gate-to-drain capacitance“Cgda” of device 1401A), the voltage on the output node (i.e., the inputof the next stage, IN1) will increase by the capacitive divider createdby Cgda and Cin, where Cin is the input capacitance of the next stage(e.g., C1in and C2 in of FIG. 14B, which are typically about the samevalue). However, by applying a complementary signal to the gate of thedummy device 1401B, which is coupled to the output node through bothgate-to-drain capacitor Cgdb and gate-to-source capacitor Cgsb, theeffects of the capacitive divider may be cancelled out. For example, asmentioned above, device 1401B is one-half the size of device 1401A.Therefore, the capacitances are related as follows:

Cgda=Cgsb+Cgdb

Accordingly, the increase in voltage caused by capacitive divider Cgdaand Cin is cancelled by the decrease in voltage caused by capacitivedivider (Cgsb∥Cgdb) and Cin. Thus, using the techniques described above,the effects of charge injection and switching feedthrough may bereduced.

FIG. 15 illustrates another embodiment of the present invention. In manyapplications it may be desirable to control the amplitude of a signal inaddition to removing DC offset. The present invention advantageouslycalibrates the DC offset before modifying the amplitude so that any suchchanges in the amplitude will be free of DC offset. Accordingly, the DCoffset will not change as the amplitude of the signal is changed.Additionally, it may be desirable to tune the amplitude of the signalbefore the VGA (or PGA) so that the performance of the VGA (or PGA) isoptimized. Offset cancellation circuits according to some embodiments ofthe present invention may include DC offset cancellation stages withvariable attenuation. Each DC offset cancellation stage may include ahigh pass filter with variable attenuation, for example. In thisexample, the DC offset cancellation circuit includes three stages withvariable attenuation 1505-1507 arranged in parallel so that DC offsetmay be reduced for different LO frequencies and the attenuation of theAC signal may be controlled. Stages 1505-1507 are coupled to the inputof VGA 1515. Attenuation may be controlled by control signals receivedfrom a channel and attenuation control circuit (not shown). Variableattenuation may allow the system to control the strength of the signalapplied to the input of the VGA so that the amplification by VGA 1515 isoptimized for the range of ADC 1516.

FIG. 16 is an example implementation of DC offset cancellation stageswith variable attenuation according to another embodiment of the presentinvention. The output of mixer 1612 is coupled through filter 1614 to athree stage DC offset cancellation circuit for removing DC offsetassociated with three different LO frequencies. The DC offsetcancellation circuit includes three capacitors (“C1, C2, C3”) 1604-1606that are coupled through switches 1601-1603, respectively, and aresistance to ground. In this case, the resistance includes a variableattenuator (“R1”) 1607 and a second resistor (“R2”) 1608. Resistor R2may be switched in parallel with attenuator R1 using switch 1609 toreduce the time constant of each stage during a DC offset calibrationcycle. Thus, switches 1601-1603 and switch 1609 may be used toselectively store three DC offsets corresponding to three different LOfrequencies on capacitors C1-C3. Variable attenuator 1607 may receivecontrol signals (not shown), such as digital signals, for opening andclosing switches for changing the attenuation of the circuit. In oneembodiment, the variable attenuator may use the techniques disclosed incommonly-owned concurrently filed U.S. patent application Ser. No.______ (Unassigned, Attorney Docket No. 000007-000900US), entitledWIDEBAND ATTENUATOR CIRCUITS AND METHODS, naming Edris Rostami, RahimBagheri, and Masoud Djafari as inventors, the entire disclosure of whichis hereby incorporated herein by reference. The output is provided to anamplifier 1615, which may be the first stage of a VGA, for example. Asillustrated previously, the present invention may be implemented as adifferential circuit.

FIG. 17 illustrates a variable gain amplifier circuit (“VGA”) 1700according to one embodiment of the present invention. VGA 1700 may be aprogrammable gain amplifier (“PGA”) that receives digital signals forchanging the total gain of the circuit in incremental steps. VGA 1700receives an input signal in a first amplification stage 1710. Theamplified output is received by a first DC offset cancellation andvariable attenuation circuit 1720. The second stage of VGA 1700 receivesthe output of circuit 1720 and includes amplifier 1730 and a second DCoffset cancellation and variable attenuation circuit 1740. In oneembodiment, amplifiers 1710 and 1730 are fixed gain amplifiers, and thetotal gain of the VGA is controlled by changing the attenuation ofvariable attenuators in circuits 1720 and 1740 using control signalincluded in Vctr11 and Vctr12. Moreover, in some embodiments, circuits1720 and 1740 may receive control signals Vctr11 and Vctr12,respectively, to reconfigure each circuit into two different states. Ina first state, each circuit has a lower time constant for storing DCoffset on an internal capacitance in a shorter amount of time. In asecond state, each circuit has a lower cutoff frequency for passing allfrequencies of interest. In one embodiment, the present inventionadvantageously calibrates the DC offset before modifying the amplitude.For example, each stage of the VGA may include a fixed gain amplifier, aDC offset calibration circuit and a variable attenuator coupled inseries. Amplification and DC offset calibration are placed before thevariable attenuator so that any such changes in the amplitude will notDC offset. Thus, the DC offset correction will not be affected by gainvariations, as might be the case if the gain adjustment were before theDC calibration.

FIG. 18A illustrates part of a VGA 1800A with a DC offset cancellationcircuit 1830 according to one embodiment of the present invention. VGA1800A receives input signals in amplifier 1810 and couples the amplifiedsignals to DC offset cancellation circuit 1830. Amplifier 1810 mayintroduce DC offset, and may further amplify any DC offset received atit's input from prior circuitry. DC offset correction circuit 1830includes a capacitor (“C2”) 1831 for storing DC offset from amplifier1810. Capacitor C2 is coupled through a resistor 1833 to ground.Resistor 1833 may be a variable attenuator, for example. In someembodiments, such as during the reception of symbols described above, DCoffset calibration may need to occur over a short time period. Thus, DCoffset calibration circuit 1830 includes a second resistor 1832 that maybe configured in parallel with resistor 1833 by closing switch 1834, forexample. When resistors 1832 and 1833 are in parallel, the RC timeconstant of the circuit is reduced (i.e., the low cutoff frequency isincreased), and the time it takes for capacitor C2 to discharge toground is reduced. Switch 1834 may then be opened to reconfigure thecircuit to have a lower cutoff frequency so all frequencies of interestmay pass. In one embodiment, resistor 1833 may be a variable attenuator.For example, resistor 1833 may be a wideband attenuator using techniquesdisclosed in commonly-owned concurrently filed U.S. patent applicationSer. No. ______ (Unassigned, Attorney Docket No. 000007-000900US),entitled WIDEBAND ATTENUATOR CIRCUITS AND METHODS, naming Edris Rostami,Rahim Bagheri, and Masoud Djafari as inventors, the entire disclosure ofwhich was incorporated herein by reference above.

While the circuit in FIG. 18A may be useful in many applications, thereis one phenomenon that may impact system performance. When switch 1834is closed, a resistor divider will be created with the output impedance,rout, of amplifier 1810 and resistors 1832-1833. This resistor dividerwill cause a variation in the gain. In some applications, the circuit ofFIG. 18A is limited because it may be desirable to have the low cutofffrequency greater than the low cutoff frequency of previous stages. Theresistor values are set by the desired low cutoff frequency and theinput capacitance of the subsequent amplifier 1850, and the value of C2is set by the low cutoff frequency during normal operation. To switchbetween 1 MHz and 25 MHz, for example, resistor 1832 should be about 25times smaller than resistor 1833. It would be desirable to add moredegrees of freedom to compensate for gain variation.

FIG. 18B illustrates part of a VGA with a DC offset cancellation circuitaccording to another embodiment of the present invention. As describedabove, one problem with circuit 1800A is that the output impedance ofamplifier 1810, together with resistors 1832 and 1833 may cause changesin the gain of the circuit when the DC offset cancellation circuitchanges from a DC offset calibration state into a normal operation state(e.g., by opening switch 1834). Large gain variation may be unacceptablein some systems. Therefore, DC offset cancellation circuit 1800Bincludes an amplifier 1810 coupled to a second stage amplifier 1850through two parallel signal paths. In a first state (e.g., a DCcalibration state), switch 1845 couples the input of amplifier 1850 to afirst DC cancellation stage 1820 having higher cutoff frequency than asecond parallel DC cancellation stage 1840. Stage 1820 includes acapacitor (“C1”) 1821 and resistor 1822. The components of stage 1820are selected to have a low RC time constant (i.e., high cornerfrequency) for storing a DC offset on capacitor 1821 in a short amountof time. Capacitor 1821 and resistor 1822 are also selected so that thecutoff frequency is still low enough to pass frequencies of interest.Thus, during a DC offset calibration, stage 1820 stores the DC offset oncapacitor 1821.

In a normal operating state, switch 1845 is reconfigured to couple theinput of amplifier 1850 to stage 1840 having a lower cutoff frequencythan stage 1820. Stage 1840 also includes a capacitor (“C2”) andresistor 1843. However, the cutoff frequency of stage 1840 is lower thanthe cutoff frequency of stage 1820 so that all frequencies of interestmay pass during normal operation. However, the DC offset correctionvoltage must be stored on this stage as well. Since this stage has alower cutoff frequency, the RC time constant set by capacitor 1841 andresistor 1843 will not allow the DC offset to be stored on capacitor C2during the DC calibration state. Thus, during DC calibration, stage 1840will be configured into a high cutoff frequency state by closing switch1844 so that the time constant of the circuit is reduced and the DCoffset may be stored on C2. Once the DC offset is stored on capacitorsC1 and C2, switch 1844 is opened and switch 1845 is reconfigured so thatsignal passes through low cutoff frequency stage 1840.

By using two stages in parallel there is a wider range of choices forthe values of R and C in each signal path. For example, because stage1820 is not switching cutoff frequencies, resistance 1822 may be lessthan resistance 1833 (i.e., resistance 1822 is reduced) and capacitance1821 may be reduced. Reducing resistance 1822 results in an increase ineffective upper bandwidth of this stage when coupled to the inputcapacitance of subsequent stages. Capacitance 1821 may also be reducedso that the effects of a capacitive divider created by capacitance 1821and the parasitic input capacitance of switch 1845 and amplifier 1850can be reduced. Similarly, because no signal is passing through stage1840, a larger resistor value may be used for resistor 1842 (i.e., alower cutoff frequency). For example, in one embodiment resistors 1822and 1843 may be about the same size and resistor 1842 may be aboutone-tenth the value of resistor 1843. Thus, the effects of the resistordivider created with the output impedance of amplifier 1810 will bereduced.

FIG. 19 illustrates wireless receiver with DC offset cancellationaccording to another embodiment of the present invention. Wirelessreceiver 1900 combines the techniques described above to achieve reducedDC offset. Wireless receiver 1900 includes an antenna 1910 for receivingRF signals, an LNA 1911 for amplifying the RF signals, a mixer 1912 fordown converting the RF signals. Mixer 1912 includes a first inputcoupled to the output of LNA 1911 for receiving the RF signal to be downconverted and a second input coupled to an LO signal. If the systemchanges channel (i.e., the carrier frequency of the RF signal changes),the LO signal may also change. In one embodiment, the LO frequencies mayhop between from about 3 GHz to about 9 GHz in about 500 Mhz intervalsso that the receiver can down convert RF signals in a number ofdifferent frequencies. In one specific example, RF signals may hopbetween three different frequencies in one of four band groups. Signalsreceived in the first band group may hop between about 3.5 GHz, 4 GHzand 4.5 GHz, signals received in the second band group may hop betweenabout 5 GHz, 5.5 GHz and 6 GHz, signals received in the third band groupmay hop between about 6.5 GHz, 7 GHz and 7.5 GHz and signals received inthe fourth band group may hop between about 8 GHz, 8.5 GHz and 9 GHz.Within each band group, the frequencies may hop in a variety of hoppingpatterns.

The output of mixer 1920 is coupled through a filter 1914 and buffer1915 to the input of a DC offset cancellation circuit 1901. The outputof buffer 1920 is coupled to three parallel DC offset cancellationstages, which in this example include capacitors 1921-1923 that eachhave one terminal coupled to the output of buffer 1920 and a secondterminal coupled to three switches 1927-1929. Switches 1927-1929 mayalso include dummy devices (not shown) for reducing charge injectioneffects. Switches 1927-1929 are coupled to variable attenuator (“R1”)1925 and resistor (“R2”) 1924. DC offset cancellation circuit 1901 mayreceive control signals from a control circuit 1980 for reconfiguringthe circuit between states and controlling the attenuation in variableattenuator 1925. For example, control circuit 1980 may transmit controlsignals to close switches 1927 and 1926 during a first time period of aninput signal received on a first carrier frequency (e.g., during a firstportion of an incoming symbol) so that the DC offset associated with theLO signal used to down convert the RF input is stored on capacitor C1.Similarly, control circuit 1980 may reconfigure the circuit by openingswitch 1926 during a second time period of the input signal so that thecutoff frequency is reduced and more frequencies may pass. When the LOchanges frequency, control circuit 1980 may generate control signals forchanging between stages (e.g., opening switch 1927 and closing eitherswitch 1928 or switch 1929). If filter 1914 causes transients or ringingat its output, the switches 1927-1928 may be opened for a predeterminedtime interval so that such ringing does not corrupt the stored DCcalibration values on the capacitors.

The output of DC offset cancellation circuit 1901 is coupled to theinput of VGA 1902. VGA 1902 includes a first fixed gain amplifier 1930,a first DC offset cancellation circuit and attenuator 1931, a secondfixed gain amplifier 1940, a second DC offset cancellation circuit andattenuator 1941 and a final fixed gain amplifier 1950. The DC offsetcancellation circuits 1931 and 1941 include internal capacitances forstoring DC offsets from amplifiers 1930 and 1940, respectively. DCoffset cancellation circuit and attenuators 1931 and 1941 may receivecontrol signals from control circuit 1980 for reconfiguring the circuitsbetween states and controlling the attenuation of the variableattenuators. For example, control circuit 1980 may transmit controlsignals to lower the time constant of each circuits during a first timeperiod that an input signal received (e.g., during a first portion ofthe first incoming symbol) so that the DC offset associated amplifier1930 is reduced. Similarly, control circuit 1980 may reconfigure thecircuit and lower the cutoff frequency during a second time period sothat more frequencies may pass. Control circuit 1980 may also providecontrol signals for selecting between first and second signals paths,wherein a first signal path has a low time constant and a second signalpath has a low cutoff frequency. Control circuit 1980 may also providecontrol signals to control the attenuation of each attenuator. In oneembodiment, each of the attenuators may use techniques disclosed indisclosed in commonly-owned concurrently filed U.S. patent applicationSer. No. ______ (Unassigned, Attorney Docket No. 000007-000900US),entitled WIDEBAND ATTENUATOR CIRCUITS AND METHODS, naming Edris Rostami,Rahim Bagheri, and Masoud Djafari as inventors, the entire disclosure ofwhich was incorporated herein by reference above.

In this example, DC offset cancellation circuits in VGA 1902 are used inconjunction with DC cancellation circuit 1901 between the filter andVGA. In one embodiment, the stages of DC offset cancellation circuit1901 have cutoff frequencies that are less than the cutoff frequency ofthe DC offset cancellation circuits in the VGA so that the VGA circuitscan track the signals from the previous stages during a DC calibration.For example, in one embodiment, the DC offset cancellation circuits inthe VGA have a low cutoff frequency about twice the cutoff frequency ofthe upstream DC offset cancellation stages. In particular, if the lowcutoff frequency of each DC offset cancellation stage may be 15 Mhz, thelow cutoff frequency of the DC offset cancellation circuits in the VGAmay be 30 Mhz, for example.

The above description illustrates various embodiments of the presentinvention along with examples of how aspects of the present inventionmay be implemented. The above examples and embodiments should not bedeemed to be the only embodiments, and are presented to illustrate theflexibility and advantages of the present invention as defined by thefollowing claims. Based on the above disclosure and the followingclaims, other arrangements, embodiments, implementations and equivalentswill be evident to those skilled in the art and may be employed withoutdeparting from the spirit and scope of the invention as defined by theclaims. The terms and expressions that have been employed here are usedto describe the various embodiments and examples. These terms andexpressions are not to be construed as excluding equivalents of thefeatures shown and described, or portions thereof, it being recognizedthat various modifications are possible within the scope of the appendedclaims.

1. A wireless receiver comprising: a mixer having a first input, asecond input and an output, wherein the first input is coupled to afirst amplifier to receive an amplified RF signal and the second inputis coupled to a frequency synthesizer to receive a first signal havingone of a plurality of frequencies; and a plurality of parallel DC offsetcancellation stages selectively coupled to the mixer output, wherein ifthe first signal has a first frequency, then a first one of theplurality of parallel DC offset cancellation stages is coupled to themixer output, and if the first signal has a second frequency, then asecond one of the plurality of parallel DC offset cancellation stages iscoupled to the mixer output.
 2. The wireless receiver of claim 1wherein, in a first state, at least one of the DC offset cancellationstages has a first low cutoff frequency and, in a second state, the atleast one DC offset cancellation stage has a second low cutoff frequencyless than the first low cutoff frequency.
 3. The wireless receiver ofclaim 1 wherein each of the plurality of DC offset cancellation stagesincludes a switch and a capacitor.
 4. The wireless receiver of claim 1wherein the DC offset cancellation stages comprise high pass filters. 5.The wireless receiver of claim 4 wherein the high pass filters areconfigure to have a first cutoff frequency during a calibration phaseand a second cutoff frequency during normal operation.
 6. The wirelessreceiver of claim 4 wherein the high pass filters are configure to havea first cutoff frequency during a first portion of a symbol and a secondcutoff frequency during a second portion of a symbol.
 7. A wirelessreceiver comprising a DC offset cancellation circuit, wherein thewireless receiver demodulates an RF signal using a plurality ofdifferent local oscillator frequencies at different times, and whereinthe DC offset cancellation circuit stores a plurality of DC voltagescorresponding to the plurality of different local oscillatorfrequencies.
 8. The wireless receiver of claim 11 wherein the DC offsetcancellation circuit is coupled between a mixer and a variable gainamplifier.
 9. The wireless receiver of claim 12 wherein the variablegain amplifier includes at least one second DC offset cancellationcircuit, wherein in the first state, the second DC offset cancellationcircuit has a third low cutoff frequency greater than the first lowcutoff frequency of the first DC offset cancellation circuit, and in thesecond state, the second DC offset cancellation circuit has a fourth lowcutoff frequency less than the third low cutoff frequency.
 10. Thewireless receiver of claim 11 further comprising a variable gainamplifier comprising a fixed gain amplifier and variable attenuator,wherein the first DC cancellation circuit is coupled between the fixedgain amplifier and the variable attenuator.
 11. The wireless receiver ofclaim 11 wherein the DC cancellation circuit includes a first and secondparallel DC cancellation stages.
 12. A method comprising: receiving anRF signal at a first input of a mixer; receiving a local oscillatorsignal at a second input of a mixer, the local oscillator signal havinga first frequency; generating a first signal at an output of the mixer;coupling the first signal to a first DC offset cancellation stage;changing the frequency of the local oscillator signal, and in accordancetherewith, coupling the first signal to a second DC offset cancellationstage.
 13. The method of claim 12 further comprising storing, in each DCoffset cancellation stage, a DC offset voltage corresponding to afrequency of the local oscillator signal.
 14. A method of cancelling DCoffset in a wireless receiver comprising: storing a first DC voltagewhen said wireless receiver demodulates an RF signal using a first localoscillator frequency; and storing a second DC voltage when the wirelessreceiver demodulates an RF signal using a second local oscillatorfrequency.
 15. The method of claim 14 wherein the wireless receivergenerates one or more additional local oscillator frequencies fordemodulating the RF signal, the method further comprising storing one ormore DC additional offset voltages corresponding to the one or moreadditional local oscillator frequencies.
 16. The method of claim 15wherein the local oscillator frequencies change between differentfrequencies according to a pattern.
 17. The method of claim 14 whereinthe local oscillator frequencies change periodically.
 18. The method ofclaim 14 further comprising configuring a DC cancellation circuit tohave a first low cutoff frequency during a calibration cycle, andconfiguring the DC cancellation circuit to have a second low cutofffrequency during normal operation.
 19. The method of claim 18 whereinthe first low cutoff frequency is higher than the second low cutofffrequency.
 20. The method of claim 14 further comprising configuring aDC cancellation circuit to have a first low cutoff frequency during afirst portion of a symbol, and configuring the DC cancellation circuitto have a second low cutoff frequency during a second portion of asymbol.